1. Field of the Invention
The present invention is directed to a multi-CPU programmable controller, and more particularly to such programmable controller having two or more controller unit including individual CPUs which operate independently from each other to access one of a plurality of I/O interface units through a common I/O bus for controlling the associated one of the equipments respectively connected to the I/O interface units.
2. Description of the Prior Art
A multi-CPU Programmable controller having two or more CPUs, already known in the art, is designed to include a master controller unit with a master CPU [referred to as master CPU unit] and one or more slave CPU controller units with individual slave CPUs [referred to as salve CPU unit]. In this conventional system, the master CPU unit is responsible for managing to operate a plurality of I/O interface units over the slave CPU unit or units for controlling equipments or control devices connected respectively to the I/O interface units. For example, when activating the equipments, the master CPU unit collects data from the slave CPU unit or units through a common memory for operating the I/O interface units based upon thus collected date. When, on the other hand, making data-input to the master and slave CPU units, the master CPU unit is also responsible for respectively collecting data from the individual equipments through the I/O interface unit and distributing the data to the slave CPU units through the common memory. In this prior system, therefore, the slave CPU unit is not allowed to control the I/O interface units or the associated equipments independently of the master CPU unit. Consequently, the prior system suffers from the following drawbacks.
1) The master CPU units is required to have increased burden for the control of the I/O interface units; and PA1 2) The slave CPU is disabled when the master CPU is stopped.
Further, it is possible to provide another programmable controller with two controller units with individual CPUs in which the two controller units operate alternately as a master CPU unit and a slave CPU unit for controlling a plurality of I/O interface units and corresponding equipments or control devices connected thereto through a common I/O bus. In this system, however, the slave CPU unit is required to monitor the master CPU unit accessing the I/O interface unit in order to take over and access instead the corresponding I/O interface unit through the common I/O bus. This is possible only with a software monitoring the status of the CPU units and therefore suffers from a loss time in arbitrating between the CPU units.